The present invention generally pertains to subscriber communications systems and is particularly directed to an improved subscriber unit for wireless communication with a base station in a wireless digital subscriber communication system.
A typical subscriber unit is described in U.S. patent application Ser. No. 06/893,916 filed Aug. 7, 1986 by David N. Critchlow et al., now U.S. Pat. No. 4,825,448. A base station used with such a subscriber unit in a wireless digital subscriber communication system is described in U.S. Pat. No. 4.777,633 to Thomas E. Fietcher, Wendeline R. Avis, Gregory T. Saffee and Karle J. Johnson. The subscriber unit described in U.S. Pat. No. 4,825,448 includes means for transcoding a digital voice input signal to provide digital input symbols; means for FIR filtering the digital input symbols; means for deriving an analog intermediate frequency input signal from the filtered input symbols; means for combining the intermediate frequency input signal with an RF carrier for radio transmission to the base station; means for demodulating an output signal received from the base station to provide digital output symbols; and means for synthesizing a digital voice output signal from the digital output symbols. The subscriber unit includes a baseband processor chip and a modem processor chip. Both are TMS32020 digital signal processors. The baseband processor chips perform the transcoding of the digital voice input signal, the synthesis of the digital output symbols, and various baseband control functions: and the modem processor chip performs the FIR filtering of the digital input symbols, and the demodulation of the output signal received from the base station. The modem processor chip generally acts as the master for the system.
The present invention provides a less expensive subscriber unit. The subscriber unit of the present invention includes means for transcoding a digital voice input signal to provide digital input symbols: means for FIR filtering the digital input symbols; means for modulating a digital intermediate frequency signal with the filtered input symbols to provide a modulated intermediate frequency input signal; means for processing the modulated input signal for transmission to the base station; means for demodulating an output signal received from the base station to provide digital output symbols; and means for synthesizing a digital voice output signal from the digital output symbols; wherein the subscriber unit includes a FIR chip for performing said FIR filtering of the digital input symbols; a DIF chip for digitally synthesizing said digital intermediate frequency signal and for performing said modulation of said digital intermediate frequency signal; and a single processor chip for performing said transcoding of said digital voice input signal, for performing said demodulation of said output signal received from the base station, and for performing said synthesizing of the digital output symbols.
The FIR chip performs the FIR filtering function that was implemented by software in the modem processor of the prior art subscriber unit described above. By moving the time consuming transmit FIR filtering function out of the modem processor and by performing the demodulation function with the same processor that performs the baseband processing function, only one processor chip is required.
The means for digitally synthesizing the digital intermediate frequency signal is a direct digital synthesizer (DDS) which include means coupled to the processor chip for accumulating phase data provided by the processor chip to indicate a predetermined intermediate frequency; and means for processing the accumulated phase data to generate said digital intermediate frequency signal at the predetermined intermediate frequency. The present invention thus adds new functionality to the subscriber unit which did not exist in the prior art subscriber unit described above in that direct digital synthesis enables extremely flexible tuning of the subscriber unit. In the prior art subscriber unit described above, tuning was restricted to a finite set of channels spaced at 25 KHz increments. Also the frequency difference between transmit and receive was fixed at 5 MHz. The DOS function of the DIF chip removes these limitations, thereby allowing other types of channel spacings or TX/RX offsets to be supported with minimal or no modification to the subscriber unit hardware.
Accordingly the DIF chip provides a fully modulated digital IF signal that can be digitally synthesized at any one of a plurality of different predetermined IF frequencies; and fine resolution frequency adjustment can be provided in the DIF chip to allow frequency tracking of the output signal received from the base station. These two features allow the radio of the subscriber unit to contain only a fixed frequency LO reference and eliminates the requirement of an RF synthesizer. These two features also allow the primary frequency reference in the subscriber unit to be fixed, with all tuning adjustments being performed by the DIF chip.
A direct digital synthesizer is stable and easy to produce. Phase noise specifications can be met without the need for an expensive and complex PLL RF synthesizer. The DOS feature provides frequency agility within the IF band and provides easier frequency modifications for operation in other bands.
Another feature of the present invention is that the FIR chip includes means for generating timing signals for timing the transcoding operation and the operation of synthesizing the digital voice output signal by the processor chip.
However, the processor chip performs the demodulation of the output signal received from the base station independently of the timing signals generated by, the FIR chip. The processor chip receives said output signal in accordance with the timing signals generated by the FIR chip, and buffers the received output signal for demodulation, thereby allowing the processor chip to perform said demodulation when not performing said transcoding and synthesizing operations.
The present invention also reduces manufacturing costs by including a combination of a slow memory coupled to the processor chip for storing processing codes used by the processor chip when said codes need not be operated with zero wait states; and a fast memory coupled to the processor chip for temporarily storing processing codes used by the processor chip when said codes are operated with zero wait states. Fast RAMs (with a zero wait state) and fast EPROMs with the same chip density are very expensive. In order to reduce costs, the processor codes can be stored in a slow EPROM (with one or more wait states), and when procedures must be run with zero wait states, the code can be uploaded from the slow memory to the fast memory and run from there.
Additional features of the present invention are described in relation to the description of the preferred embodiment.